Project Settings
Project Name Eval_pfm_top_syn Implementation Name synthesis
Top Module work.Eval_pfm_top Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 83 540 0 - 0m:09s - 2/1/2017
6:24:36 PM
(premap)Complete 65 13 0 0m:02s 0m:01s 169MB 2/1/2017
6:24:40 PM
(fpga_mapper)Complete 344 53 0 0m:40s 0m:40s 261MB 2/1/2017
6:25:21 PM
Multi-srs Generator Complete0m:01s2/1/2017
6:24:38 PM

Area Summary
Carry Cells 189 Sequential Cells 3323
DSP Blocks (MACC) (dsp_used) 0 I/O Cells 65
Global Clock Buffers 9 LUTs (total_luts) 4222

Timing Summary
Clock NameReq FreqEst FreqSlack
Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock100.0 MHz132.2 MHz1.219
Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock100.0 MHz372.7 MHz7.317
Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock100.0 MHz100.9 MHz0.084
System100.0 MHz895.2 MHz8.883

Optimizations Summary
Combined Clock Conversion 2 / 1