#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 8 6.2 #Hostname: ELITEBOOK8440P #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys VHDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : Eval_pfm_top.vhd(17) | Top entity is set to Eval_pfm_top. File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_MSS\Eval_pfm_MSS_syn.vhd changed - recompiling File C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_addrdec.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_defaultslavesm.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavearbiter.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_pkg.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\components.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_top\FCCC_0\Eval_pfm_top_FCCC_0_FCCC.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_top\IO_10\Eval_pfm_top_IO_10_IO.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ascon_fast_core.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ahb_reg.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\RAM_if.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\text_process.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vhdl\core\coreresetp.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_MSS\Eval_pfm_MSS.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm\OSC_0\Eval_pfm_OSC_0_OSC.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_masterstage.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_slavestage.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite_matrix4x16.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vhdl\core\coreahblite.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm\Eval_pfm.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_top\OSC_0\Eval_pfm_top_OSC_0_OSC.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ascon_fast_bus.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ctrl.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\component\work\Eval_pfm_top\Eval_pfm_top.vhd changed - recompiling VHDL syntax check successful! File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ahb_reg.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\RAM_if.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\text_process.vhd changed - recompiling File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\hdl\ctrl.vhd changed - recompiling @N:CD630 : Eval_pfm_top.vhd(17) | Synthesizing work.eval_pfm_top.rtl @N:CD630 : text_process.vhd(32) | Synthesizing work.text_process.architecture_text_process @N:CD233 : text_process.vhd(57) | Using sequential encoding for type proc_st_type Post processing for work.text_process.architecture_text_process @N:CD630 : Eval_pfm_top_OSC_0_OSC.vhd(8) | Synthesizing work.eval_pfm_top_osc_0_osc.def_arch @N:CD630 : osc_comps.vhd(39) | Synthesizing work.xtlosc.def_arch Post processing for work.xtlosc.def_arch @N:CD630 : osc_comps.vhd(19) | Synthesizing work.rcosc_25_50mhz.def_arch Post processing for work.rcosc_25_50mhz.def_arch Post processing for work.eval_pfm_top_osc_0_osc.def_arch @W:CL240 : Eval_pfm_top_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_top_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_top_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_top_OSC_0_OSC.vhd(12) | RCOSC_25_50MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_top_OSC_0_OSC.vhd(11) | RCOSC_25_50MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL168 : Eval_pfm_top_OSC_0_OSC.vhd(43) | Pruning instance I_RCOSC_25_50MHZ -- not in use ... @N:CD630 : Eval_pfm_top_IO_10_IO.vhd(8) | Synthesizing work.eval_pfm_top_io_10_io.def_arch @N:CD630 : smartfusion2.vhd(413) | Synthesizing smartfusion2.outbuf.syn_black_box Post processing for smartfusion2.outbuf.syn_black_box Post processing for work.eval_pfm_top_io_10_io.def_arch @N:CD630 : Eval_pfm_top_FCCC_0_FCCC.vhd(8) | Synthesizing work.eval_pfm_top_fccc_0_fccc.def_arch @N:CD630 : smartfusion2.vhd(794) | Synthesizing smartfusion2.ccc.syn_black_box Post processing for smartfusion2.ccc.syn_black_box @N:CD630 : smartfusion2.vhd(562) | Synthesizing smartfusion2.clkint.syn_black_box Post processing for smartfusion2.clkint.syn_black_box @N:CD630 : smartfusion2.vhd(576) | Synthesizing smartfusion2.gnd.syn_black_box Post processing for smartfusion2.gnd.syn_black_box @N:CD630 : smartfusion2.vhd(582) | Synthesizing smartfusion2.vcc.syn_black_box Post processing for smartfusion2.vcc.syn_black_box Post processing for work.eval_pfm_top_fccc_0_fccc.def_arch @N:CD630 : Eval_pfm.vhd(20) | Synthesizing work.eval_pfm.rtl @W:CD638 : Eval_pfm.vhd(470) | Signal coreconfigp_0_soft_fddr_core_reset is undriven @N:CD630 : smartfusion2.vhd(786) | Synthesizing smartfusion2.sysreset.syn_black_box Post processing for smartfusion2.sysreset.syn_black_box @N:CD630 : Eval_pfm_OSC_0_OSC.vhd(8) | Synthesizing work.eval_pfm_osc_0_osc.def_arch @N:CD630 : osc_comps.vhd(79) | Synthesizing work.rcosc_25_50mhz_fab.def_arch Post processing for work.rcosc_25_50mhz_fab.def_arch Post processing for work.eval_pfm_osc_0_osc.def_arch @W:CL240 : Eval_pfm_OSC_0_OSC.vhd(16) | XTLOSC_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_OSC_0_OSC.vhd(15) | XTLOSC_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_OSC_0_OSC.vhd(14) | RCOSC_1MHZ_O2F is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_OSC_0_OSC.vhd(13) | RCOSC_1MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : Eval_pfm_OSC_0_OSC.vhd(11) | RCOSC_25_50MHZ_CCC is not assigned a value (floating) -- simulation mismatch possible. @N:CD630 : Eval_pfm_MSS.vhd(17) | Synthesizing work.eval_pfm_mss.rtl @N:CD630 : smartfusion2.vhd(503) | Synthesizing smartfusion2.outbuf_diff.syn_black_box Post processing for smartfusion2.outbuf_diff.syn_black_box @N:CD630 : smartfusion2.vhd(434) | Synthesizing smartfusion2.bibuf.syn_black_box Post processing for smartfusion2.bibuf.syn_black_box @N:CD630 : smartfusion2.vhd(403) | Synthesizing smartfusion2.inbuf.syn_black_box Post processing for smartfusion2.inbuf.syn_black_box @N:CD630 : smartfusion2.vhd(423) | Synthesizing smartfusion2.tribuff.syn_black_box Post processing for smartfusion2.tribuff.syn_black_box @N:CD630 : Eval_pfm_MSS_syn.vhd(10) | Synthesizing work.mss_025.def_arch Post processing for work.mss_025.def_arch Post processing for work.eval_pfm_mss.rtl @N:CD630 : coreresetp.vhd(27) | Synthesizing work.coreresetp.rtl Post processing for work.coreresetp.rtl @W:CL169 : coreresetp.vhd(1495) | Pruning register count_sdif3_2(12 downto 0) @W:CL169 : coreresetp.vhd(1471) | Pruning register count_sdif2_2(12 downto 0) @W:CL169 : coreresetp.vhd(1447) | Pruning register count_sdif1_2(12 downto 0) @W:CL169 : coreresetp.vhd(1423) | Pruning register count_sdif0_2(12 downto 0) @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_rcosc_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif3_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif2_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif1_enable_q1_2 @W:CL169 : coreresetp.vhd(1395) | Pruning register count_sdif0_enable_q1_2 @W:CL169 : coreresetp.vhd(1311) | Pruning register count_sdif3_enable_3 @W:CL169 : coreresetp.vhd(1252) | Pruning register count_sdif2_enable_3 @W:CL169 : coreresetp.vhd(1193) | Pruning register count_sdif1_enable_3 @W:CL169 : coreresetp.vhd(1134) | Pruning register count_sdif0_enable_3 @N:CL177 : coreresetp.vhd(1331) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q1. @W:CL190 : coreresetp.vhd(1376) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.vhd(1059) | Pruning register release_ext_reset @W:CL169 : coreresetp.vhd(1376) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.vhd(1376) | Pruning register sm2_state(2 downto 0) @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.vhd(792) | Pruning register sm2_areset_n_clk_base @N:CD630 : coreconfigp.vhd(26) | Synthesizing work.coreconfigp.rtl Post processing for work.coreconfigp.rtl @N:CD630 : coreahblite.vhd(27) | Synthesizing coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite_matrix4x16.vhd(25) | Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch @N:CD630 : coreahblite_slavestage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_slavearbiter.vhd(22) | Synthesizing coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch @W:CD604 : coreahblite_slavearbiter.vhd(391) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_slavearbiter.coreahblite_slavearbiter_arch Post processing for coreahblite_lib.coreahblite_slavestage.trans @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(339) | Signal sdataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(340) | Signal shresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hrdata_s16 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hreadyout_s16 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_defaultslavesm.vhd(22) | Synthesizing coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @W:CD604 : coreahblite_defaultslavesm.vhd(63) | OTHERS clause is not synthesized Post processing for coreahblite_lib.coreahblite_defaultslavesm.coreahblite_defaultslavesm_arch @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. Post processing for coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch Post processing for coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite.vhd(27) | Synthesizing coreahblite_lib.coreahblite.coreahblite_arch @N:CD630 : coreahblite_matrix4x16.vhd(25) | Synthesizing coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(339) | Signal sdataready in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(340) | Signal shresp in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hrdata_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(341) | Signal hreadyout_s0 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hrdata_s16 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hreadyout_s16 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. @N:CD630 : coreahblite_masterstage.vhd(24) | Synthesizing coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hrdata_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(342) | Signal hreadyout_s1 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hrdata_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(343) | Signal hreadyout_s2 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hrdata_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(344) | Signal hreadyout_s3 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hrdata_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(345) | Signal hreadyout_s4 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hrdata_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(346) | Signal hreadyout_s5 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hrdata_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(347) | Signal hreadyout_s6 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hrdata_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(348) | Signal hreadyout_s7 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hrdata_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(349) | Signal hreadyout_s8 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hrdata_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(350) | Signal hreadyout_s9 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hrdata_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(351) | Signal hreadyout_s10 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hrdata_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(352) | Signal hreadyout_s11 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hrdata_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(353) | Signal hreadyout_s12 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hrdata_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(354) | Signal hreadyout_s13 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hrdata_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(355) | Signal hreadyout_s14 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hrdata_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(356) | Signal hreadyout_s15 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hrdata_s16 in the sensitivity list is not used in the process @W:CD434 : coreahblite_masterstage.vhd(357) | Signal hreadyout_s16 in the sensitivity list is not used in the process @W:CD604 : coreahblite_masterstage.vhd(637) | OTHERS clause is not synthesized @N:CD630 : coreahblite_addrdec.vhd(50) | Synthesizing coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_addrdec.coreahblite_addrdec_arch Post processing for coreahblite_lib.coreahblite_masterstage.coreahblite_masterstage_arch @N:CL177 : coreahblite_masterstage.vhd(644) | Sharing sequential element addrRegSMCurrentState. Post processing for coreahblite_lib.coreahblite_matrix4x16.coreahblite_matrix4x16_arch Post processing for coreahblite_lib.coreahblite.coreahblite_arch Post processing for work.eval_pfm.rtl @W:CL240 : Eval_pfm.vhd(470) | CoreConfigP_0_SOFT_FDDR_CORE_RESET is not assigned a value (floating) -- simulation mismatch possible. @W:CL167 : Eval_pfm.vhd(1762) | Input soft_fddr_core_reset of instance CoreResetP_0 is floating @N:CD630 : ctrl.vhd(52) | Synthesizing work.ctrl.architecture_ctrl @N:CD233 : ctrl.vhd(233) | Using sequential encoding for type cmd_state_type @N:CD231 : ctrl.vhd(283) | Using onehot encoding for type op_state_type (op_idle="1000000") @N:CD231 : ctrl.vhd(347) | Using onehot encoding for type cipher_state_type (cipher_idle="10000000") @W:CD326 : ctrl.vhd(365) | Port ram_stg of entity work.ram_if is unconnected @W:CD274 : ctrl.vhd(639) | Incomplete case statement - add more cases or a when others @W:CD638 : ctrl.vhd(317) | Signal rd_buf_ne is undriven @W:CD638 : ctrl.vhd(358) | Signal data_from_cipher is undriven @N:CD630 : ahb_reg.vhd(65) | Synthesizing work.ahb_reg.ahb_reg @N:CD233 : ahb_reg.vhd(137) | Using sequential encoding for type ahb_state_states Post processing for work.ahb_reg.ahb_reg @A:CL282 : ahb_reg.vhd(164) | Feedback mux created for signal int_addr[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : RAM_if.vhd(47) | Synthesizing work.ram_if.ram_if @N:CD231 : RAM_if.vhd(121) | Using onehot encoding for type ram_if_states_def (idle="1000000") Post processing for work.ram_if.ram_if @A:CL282 : RAM_if.vhd(168) | Feedback mux created for signal haddr_end[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. Post processing for work.ctrl.architecture_ctrl @W:CL169 : ctrl.vhd(445) | Pruning register mux_out_5 @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal wstart_addr[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal wbytes[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal rstart_addr[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal ram_cnt[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal act_words[2:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal my_word[255:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal ram_addr[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal ram_rw -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(492) | Feedback mux created for signal ram_in[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(630) | Feedback mux created for signal TagxDI[127:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @A:CL282 : ctrl.vhd(630) | Feedback mux created for signal CiphertextxDI[127:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL190 : ctrl.vhd(630) | Optimizing register bit address_out(5) to a constant 0 @W:CL190 : ctrl.vhd(630) | Optimizing register bit address_out(6) to a constant 0 @W:CL190 : ctrl.vhd(630) | Optimizing register bit address_out(7) to a constant 0 @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(6) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(7) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(8) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(9) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(10) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(11) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(12) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(13) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(14) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(15) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(16) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(17) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(18) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(19) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(20) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(21) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(22) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(23) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(24) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(25) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(26) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(27) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(28) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(29) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(30) is always 0, optimizing ... @W:CL189 : ctrl.vhd(492) | Register bit ram_cnt(31) is always 0, optimizing ... @W:CL279 : ctrl.vhd(492) | Pruning register bits 31 to 6 of ram_cnt(31 downto 0) @W:CL279 : ctrl.vhd(630) | Pruning register bits 7 to 5 of address_out(7 downto 0) @N:CD630 : ascon_fast_bus.vhd(36) | Synthesizing work.ascon.structural @N:CD630 : ascon_fast_core.vhd(38) | Synthesizing work.ascon_core.structural @W:CD434 : ascon_fast_core.vhd(156) | Signal dp_roundxsp in the sensitivity list is not used in the process @W:CD434 : ascon_fast_core.vhd(216) | Signal dp_writeiodataxsi in the sensitivity list is not used in the process Post processing for work.ascon_core.structural @W:CL169 : ascon_fast_core.vhd(132) | Pruning register DP_RoundxSP_2 Post processing for work.ascon.structural Post processing for work.eval_pfm_top.rtl @W:CL246 : ascon_fast_core.vhd(53) | Input port bits 7 to 1 of addressxdi(7 downto 0) are unused @W:CL159 : ascon_fast_core.vhd(63) | Input DP_WriteIODataxSI is unused @W:CL159 : RAM_if.vhd(75) | Input hresp is unused @N:CL201 : ahb_reg.vhd(164) | Trying to extract state machine for register ahb_state Extracted state machine for register ahb_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL260 : ctrl.vhd(630) | Pruning register bit 4 of address_out(4 downto 0) @N:CL177 : ctrl.vhd(630) | Sharing sequential element CipherDonexS. @N:CL201 : ctrl.vhd(630) | Trying to extract state machine for register cipher_state Extracted state machine for register cipher_state State machine has 6 reachable states with original encodings of: 00000001 00000100 00001000 00100000 01000000 10000000 @N:CL201 : ctrl.vhd(492) | Trying to extract state machine for register op_state Extracted state machine for register op_state State machine has 7 reachable states with original encodings of: 0000001 0000010 0000100 0001000 0010000 0100000 1000000 @W:CL246 : coreahblite_masterstage.vhd(45) | Input port bits 16 to 1 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(46) | Input port bits 16 to 1 of shresp(16 downto 0) are unused @W:CL159 : coreahblite_masterstage.vhd(57) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(58) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_masterstage.vhd(45) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(46) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(57) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(58) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.vhd(54) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(63) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(72) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(87) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(88) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(89) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(98) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(99) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(100) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(109) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(110) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(111) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(120) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(121) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(122) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(131) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(132) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(133) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(142) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(143) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(144) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(153) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(154) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(155) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(164) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(165) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(166) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(175) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(176) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(177) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(186) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(187) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(188) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(197) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(198) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(199) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(208) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(209) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(210) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(219) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(220) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(221) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(230) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(231) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(232) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(241) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(242) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(243) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(252) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.vhd(253) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.vhd(254) | Input HRESP_S16 is unused @W:CL247 : coreahblite.vhd(124) | Input port bit 0 of htrans_m0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(135) | Input port bit 0 of htrans_m1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(146) | Input port bit 0 of htrans_m2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(157) | Input port bit 0 of htrans_m3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(167) | Input port bit 1 of hresp_s0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(180) | Input port bit 1 of hresp_s1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(193) | Input port bit 1 of hresp_s2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(206) | Input port bit 1 of hresp_s3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(219) | Input port bit 1 of hresp_s4(1 downto 0) is unused @W:CL247 : coreahblite.vhd(232) | Input port bit 1 of hresp_s5(1 downto 0) is unused @W:CL247 : coreahblite.vhd(245) | Input port bit 1 of hresp_s6(1 downto 0) is unused @W:CL247 : coreahblite.vhd(258) | Input port bit 1 of hresp_s7(1 downto 0) is unused @W:CL247 : coreahblite.vhd(271) | Input port bit 1 of hresp_s8(1 downto 0) is unused @W:CL247 : coreahblite.vhd(284) | Input port bit 1 of hresp_s9(1 downto 0) is unused @W:CL247 : coreahblite.vhd(297) | Input port bit 1 of hresp_s10(1 downto 0) is unused @W:CL247 : coreahblite.vhd(310) | Input port bit 1 of hresp_s11(1 downto 0) is unused @W:CL247 : coreahblite.vhd(323) | Input port bit 1 of hresp_s12(1 downto 0) is unused @W:CL247 : coreahblite.vhd(336) | Input port bit 1 of hresp_s13(1 downto 0) is unused @W:CL247 : coreahblite.vhd(349) | Input port bit 1 of hresp_s14(1 downto 0) is unused @W:CL247 : coreahblite.vhd(362) | Input port bit 1 of hresp_s15(1 downto 0) is unused @W:CL247 : coreahblite.vhd(375) | Input port bit 1 of hresp_s16(1 downto 0) is unused @W:CL159 : coreahblite.vhd(127) | Input HBURST_M0 is unused @W:CL159 : coreahblite.vhd(128) | Input HPROT_M0 is unused @W:CL159 : coreahblite.vhd(138) | Input HBURST_M1 is unused @W:CL159 : coreahblite.vhd(139) | Input HPROT_M1 is unused @W:CL159 : coreahblite.vhd(149) | Input HBURST_M2 is unused @W:CL159 : coreahblite.vhd(150) | Input HPROT_M2 is unused @W:CL159 : coreahblite.vhd(160) | Input HBURST_M3 is unused @W:CL159 : coreahblite.vhd(161) | Input HPROT_M3 is unused @W:CL246 : coreahblite_masterstage.vhd(45) | Input port bits 15 to 0 of sdataready(16 downto 0) are unused @W:CL246 : coreahblite_masterstage.vhd(46) | Input port bits 15 to 0 of shresp(16 downto 0) are unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(57) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(58) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(45) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.vhd(46) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.vhd(55) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(56) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.vhd(57) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(58) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.vhd(59) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(60) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.vhd(61) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(62) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.vhd(63) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(64) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.vhd(65) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(66) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.vhd(67) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(68) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.vhd(69) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(70) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.vhd(71) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(72) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.vhd(73) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(74) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.vhd(75) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(76) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.vhd(77) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(78) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.vhd(79) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(80) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.vhd(81) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(82) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.vhd(83) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(84) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.vhd(85) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(86) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.vhd(87) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.vhd(88) | Input HREADYOUT_S16 is unused @N:CL201 : coreahblite_slavearbiter.vhd(398) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_matrix4x16.vhd(54) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(63) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(72) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(76) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(77) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(78) | Input HRESP_S0 is unused @W:CL159 : coreahblite_matrix4x16.vhd(87) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(88) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(89) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.vhd(98) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(99) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(100) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.vhd(109) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(110) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(111) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.vhd(120) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(121) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(122) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.vhd(131) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(132) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(133) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.vhd(142) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(143) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(144) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.vhd(153) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(154) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(155) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.vhd(164) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(165) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(166) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.vhd(175) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(176) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(177) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.vhd(186) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(187) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(188) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.vhd(197) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(198) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(199) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.vhd(208) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(209) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(210) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.vhd(219) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(220) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(221) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.vhd(230) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(231) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(232) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.vhd(241) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(242) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.vhd(243) | Input HRESP_S15 is unused @W:CL247 : coreahblite.vhd(124) | Input port bit 0 of htrans_m0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(135) | Input port bit 0 of htrans_m1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(146) | Input port bit 0 of htrans_m2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(157) | Input port bit 0 of htrans_m3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(167) | Input port bit 1 of hresp_s0(1 downto 0) is unused @W:CL247 : coreahblite.vhd(180) | Input port bit 1 of hresp_s1(1 downto 0) is unused @W:CL247 : coreahblite.vhd(193) | Input port bit 1 of hresp_s2(1 downto 0) is unused @W:CL247 : coreahblite.vhd(206) | Input port bit 1 of hresp_s3(1 downto 0) is unused @W:CL247 : coreahblite.vhd(219) | Input port bit 1 of hresp_s4(1 downto 0) is unused @W:CL247 : coreahblite.vhd(232) | Input port bit 1 of hresp_s5(1 downto 0) is unused @W:CL247 : coreahblite.vhd(245) | Input port bit 1 of hresp_s6(1 downto 0) is unused @W:CL247 : coreahblite.vhd(258) | Input port bit 1 of hresp_s7(1 downto 0) is unused @W:CL247 : coreahblite.vhd(271) | Input port bit 1 of hresp_s8(1 downto 0) is unused @W:CL247 : coreahblite.vhd(284) | Input port bit 1 of hresp_s9(1 downto 0) is unused @W:CL247 : coreahblite.vhd(297) | Input port bit 1 of hresp_s10(1 downto 0) is unused @W:CL247 : coreahblite.vhd(310) | Input port bit 1 of hresp_s11(1 downto 0) is unused @W:CL247 : coreahblite.vhd(323) | Input port bit 1 of hresp_s12(1 downto 0) is unused @W:CL247 : coreahblite.vhd(336) | Input port bit 1 of hresp_s13(1 downto 0) is unused @W:CL247 : coreahblite.vhd(349) | Input port bit 1 of hresp_s14(1 downto 0) is unused @W:CL247 : coreahblite.vhd(362) | Input port bit 1 of hresp_s15(1 downto 0) is unused @W:CL247 : coreahblite.vhd(375) | Input port bit 1 of hresp_s16(1 downto 0) is unused @W:CL159 : coreahblite.vhd(127) | Input HBURST_M0 is unused @W:CL159 : coreahblite.vhd(128) | Input HPROT_M0 is unused @W:CL159 : coreahblite.vhd(138) | Input HBURST_M1 is unused @W:CL159 : coreahblite.vhd(139) | Input HPROT_M1 is unused @W:CL159 : coreahblite.vhd(149) | Input HBURST_M2 is unused @W:CL159 : coreahblite.vhd(150) | Input HPROT_M2 is unused @W:CL159 : coreahblite.vhd(160) | Input HBURST_M3 is unused @W:CL159 : coreahblite.vhd(161) | Input HPROT_M3 is unused @N:CL201 : coreconfigp.vhd(517) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.vhd(936) | Sharing sequential element sdif2_spll_lock_q2. @N:CL201 : coreresetp.vhd(1311) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1252) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1193) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1134) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.vhd(1059) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.vhd(96) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.vhd(126) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(135) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(139) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(143) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.vhd(157) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.vhd(158) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.vhd(159) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.vhd(160) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.vhd(161) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.vhd(162) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.vhd(163) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.vhd(164) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.vhd(165) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.vhd(166) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.vhd(167) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.vhd(168) | Input SDIF3_PRDATA is unused @W:CL159 : Eval_pfm_OSC_0_OSC.vhd(10) | Input XTL is unused @N:CL201 : text_process.vhd(84) | Trying to extract state machine for register proc_st Extracted state machine for register proc_st State machine has 4 reachable states with original encodings of: 00 01 10 11 At c_vhdl Exit (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 136MB peak: 177MB) Process took 0h:00m:11s realtime, 0h:00m:10s cputime # Wed Dec 28 09:28:17 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Dec 28 09:28:18 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:12s realtime, 0h:00m:12s cputime # Wed Dec 28 09:28:18 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\synthesis\synwork\Eval_pfm_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Wed Dec 28 09:28:22 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: Eval_pfm_top_scck.rpt Printing clock summary report in "C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\synthesis\Eval_pfm_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 140MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 140MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 140MB) @W:BN132 : coreahblite_matrix4x16.vhd(5322) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_16, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_15 @W:BN132 : coreahblite_matrix4x16.vhd(5268) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.vhd(5214) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.vhd(5160) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.vhd(5106) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.vhd(5052) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4944) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4890) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4836) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.vhd(4782) | Removing user instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : coreconfigp.vhd(528) | Removing sequential instance FDDR_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(528) | Removing sequential instance SDIF0_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(528) | Removing sequential instance SDIF1_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(528) | Removing sequential instance SDIF2_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(528) | Removing sequential instance SDIF3_PENABLE_0 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1059) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4238) | Removing instance masterstage_1 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4311) | Removing instance masterstage_2 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4384) | Removing instance masterstage_3 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4512) | Removing instance slavestage_1 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_0(trans) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4238) | Removing instance masterstage_1 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_3(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4311) | Removing instance masterstage_2 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_2(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4384) | Removing instance masterstage_3 of view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_0_1_0_0_1(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.vhd(4458) | Removing instance slavestage_0 of view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_3(trans) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : ram_if.vhd(168) | Removing sequential instance hsel of view:PrimLib.dffre(prim) in hierarchy view:work.ram_if(ram_if) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1134) | Removing sequential instance sdif0_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1193) | Removing sequential instance sdif1_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1252) | Removing sequential instance sdif2_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(1311) | Removing sequential instance sdif3_state[0:3] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(803) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(814) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreresetp.vhd(836) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.vhd(122) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_0(trans) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.vhd(122) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVESTAGE_3(trans) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_MASTERSTAGE_5_1_0_1_0(coreahblite_masterstage_arch) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.vhd(137) | Removing instance slave_arbiter of view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_1(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.vhd(137) | Removing instance slave_arbiter of view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_2(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance arbRegSMCurrentState[0:15] of view:PrimLib.statemachine(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_1(coreahblite_slavearbiter_arch) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance arbRegSMCurrentState[0:15] of view:PrimLib.statemachine(prim) in hierarchy view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_2(coreahblite_slavearbiter_arch) because there are no references to its outputs syn_allowed_resources : blockrams=31 set on top level netlist Eval_pfm_top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 167MB peak: 169MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------------------------------------------------- Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 System 100.0 MHz 10.000 system system_clkgroup ========================================================================================================================== @W:MT530 : ascon_fast_core.vhd(132) | Found inferred clock Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock which controls 3238 sequential elements including ascon_0.ascon_core_1.State3xDP[63:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreconfigp.vhd(517) | Found inferred clock Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PREADY_0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.vhd(1519) | Found inferred clock Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock which controls 31 sequential elements including Eval_pfm_0.CoreResetP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\synthesis\Eval_pfm_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 90MB peak: 169MB) Process took 0h:00m:03s realtime, 0h:00m:02s cputime # Wed Dec 28 09:28:27 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 150MB) @W:MO171 : coreresetp.vhd(703) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(719) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(735) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(751) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(781) | Sequential instance Eval_pfm_0.CoreResetP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(703) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(719) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(735) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(751) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(781) | Sequential instance Eval_pfm_0.CoreResetP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(703) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(719) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(735) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(751) | Sequential instance Eval_pfm_0.CoreResetP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.vhd(1331) | Sequential instance Eval_pfm_0.CoreResetP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:MO171 : coreconfigp.vhd(652) | Sequential instance Eval_pfm_0.CoreConfigP_0.SDIF_RELEASED_q1 reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.vhd(894) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sdif2_areset_n_rcosc_q1 @W:BN132 : coreresetp.vhd(883) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sdif1_areset_n_rcosc_q1 @W:BN132 : coreresetp.vhd(872) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.vhd(850) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc_q1, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.vhd(883) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif2_areset_n_rcosc, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.vhd(894) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif3_areset_n_rcosc, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.vhd(872) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif1_areset_n_rcosc, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.vhd(861) | Removing sequential instance Eval_pfm_0.CoreResetP_0.sdif0_areset_n_rcosc, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.vhd(1495) | Removing sequential instance Eval_pfm_0.CoreResetP_0.release_sdif3_core, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.release_sdif2_core @W:BN132 : coreresetp.vhd(1471) | Removing sequential instance Eval_pfm_0.CoreResetP_0.release_sdif2_core, because it is equivalent to instance Eval_pfm_0.CoreResetP_0.release_sdif1_core Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 147MB peak: 151MB) Encoding state machine op_state[0:6] (view:work.ctrl(architecture_ctrl)) original code -> new code 0000001 -> 0000001 0000010 -> 0000010 0000100 -> 0000100 0001000 -> 0001000 0010000 -> 0010000 0100000 -> 0100000 1000000 -> 1000000 Encoding state machine cipher_state[0:5] (view:work.ctrl(architecture_ctrl)) original code -> new code 00000001 -> 000 00000100 -> 001 00001000 -> 010 00100000 -> 011 01000000 -> 100 10000000 -> 101 @N:FX404 : ctrl.vhd(492) | Found addmux in view:work.ctrl(architecture_ctrl) inst un1_rstart_addr_1[31:0] from un1_rstart_addr[32:1] @N:FX404 : ctrl.vhd(492) | Found addmux in view:work.ctrl(architecture_ctrl) inst un1_wstart_addr_2[31:0] from un1_wstart_addr_1[32:1] @N:FX404 : ram_if.vhd(185) | Found addmux in view:work.ram_if(ram_if) inst haddr_t_8[31:0] from un1_haddr_t[32:1] Encoding state machine ahb_state[0:2] (view:work.ahb_reg(ahb_reg)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[2] of view:PrimLib.dffr(prim) in hierarchy view:work.Eval_pfm(rtl) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.vhd(305) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.vhd(235) | Register bit CoreAHBLite_1.matrix4x16.masterstage_0.regHSIZE[0] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[0:15] (view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_1(coreahblite_slavearbiter_arch)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[7] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[11] is always 0, optimizing ... Encoding state machine arbRegSMCurrentState[0:15] (view:coreahblite_lib.COREAHBLITE_SLAVEARBITER_0(coreahblite_slavearbiter_arch)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[3] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[7] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.vhd(398) | Register bit arbRegSMCurrentState[11] is always 0, optimizing ... Encoding state machine state[0:2] (view:work.CoreConfigP(rtl)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP(rtl) because there are no references to its outputs @W:MO160 : coreconfigp.vhd(341) | Register bit paddr[16] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[31] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[30] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[29] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[28] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[27] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[26] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[25] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[24] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[23] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[22] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[21] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[20] is always 0, optimizing ... @W:MO160 : coreconfigp.vhd(622) | Register bit FIC_2_APB_M_PRDATA_0[19] is always 0, optimizing ... Encoding state machine sm0_state[0:6] (view:work.CoreResetP(rtl)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : coreresetp.vhd(1519) | Found counter in view:work.CoreResetP(rtl) inst count_ddr[13:0] Encoding state machine proc_st[0:3] (view:work.text_process(architecture_text_process)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : text_process.vhd(84) | No possible illegal states for state machine proc_st[0:3],safe FSM implementation is disabled @N: : text_process.vhd(84) | Found counter in view:work.text_process(architecture_text_process) inst cnt[4:0] @N:BN362 : coreahblite_masterstage.vhd(235) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[12] in hierarchy view:work.Eval_pfm(rtl) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 207MB peak: 207MB) @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[13] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[12] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[4] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.vhd(122) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.masterDataInProg[2] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : text_process.vhd(84) | Removing sequential instance text_process_0.txt_type in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 192MB peak: 208MB) @N:BN362 : ram_if.vhd(168) | Removing sequential instance htrans_t[0] in hierarchy view:work.ram_if(ram_if) because there are no references to its outputs @N:BN362 : ctrl.vhd(445) | Removing sequential instance ctrl_0.txt_format in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : ctrl.vhd(630) | Removing sequential instance ctrl_0.CiphertextxDI[72] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : ctrl.vhd(630) | Removing sequential instance ctrl_0.CiphertextxDI[75] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs @N:BN362 : ctrl.vhd(630) | Removing sequential instance ctrl_0.CiphertextxDI[17] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 183MB peak: 210MB) @N:BN362 : coreahblite_slavearbiter.vhd(398) | Removing sequential instance Eval_pfm_0.CoreAHBLite_1.matrix4x16.slavestage_16.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs Starting Early Timing Optimization (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:20s; Memory used current: 184MB peak: 210MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:24s; Memory used current: 187MB peak: 210MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:25s; Memory used current: 185MB peak: 210MB) Finished preparing to map (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:28s; Memory used current: 184MB peak: 210MB) @N:BN362 : coreconfigp.vhd(341) | Removing sequential instance Eval_pfm_0.CoreConfigP_0.paddr[14] in hierarchy view:work.Eval_pfm_top(rtl) because there are no references to its outputs Finished technology mapping (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:35s; Memory used current: 228MB peak: 263MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:36s -2.62ns 4676 / 3269 2 0h:00m:36s -2.62ns 4636 / 3269 3 0h:00m:36s -1.80ns 4636 / 3269 4 0h:00m:36s -1.80ns 4636 / 3269 @N:FX271 : ascon_fast_core.vhd(132) | Instance "ascon_0.ascon_core_1.ControlStatexDP[3]" with 10 loads replicated 1 times to improve timing @N:FX271 : ascon_fast_core.vhd(132) | Instance "ascon_0.ascon_core_1.ControlStatexDP[2]" with 10 loads replicated 1 times to improve timing @N:FX271 : ascon_fast_core.vhd(132) | Instance "ascon_0.ascon_core_1.ControlStatexDP[0]" with 9 loads replicated 1 times to improve timing @N:FX271 : ascon_fast_core.vhd(132) | Instance "ascon_0.ascon_core_1.ControlStatexDP[1]" with 7 loads replicated 1 times to improve timing @N:FX271 : ram_if.vhd(311) | Instance "wr_cnti[0]" with 10 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[2]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[6]" with 4 loads replicated 1 times to improve timing @N:FX271 : ram_if.vhd(168) | Instance "wr_cnto[0]" with 9 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[16]" with 9 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[11]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[13]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[4]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[7]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(644) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.masterRegAddrSel" with 43 loads replicated 2 times to improve timing @N:FX271 : ascon_fast_bus.vhd(119) | Instance "ascon_0.CP_InitxSP" with 132 loads replicated 3 times to improve timing Timing driven replication report Added 18 Registers via timing driven replication Added 18 LUTs via timing driven replication @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[12]" with 6 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[10]" with 6 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[9]" with 4 loads replicated 1 times to improve timing @N:FX271 : coreahblite_masterstage.vhd(305) | Instance "Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt[14]" with 4 loads replicated 1 times to improve timing Timing driven replication report Added 4 Registers via timing driven replication Added 4 LUTs via timing driven replication 5 0h:00m:43s -0.56ns 4636 / 3291 6 0h:00m:44s -0.56ns 4636 / 3291 @N:FP130 : | Promoting Net N_2332 on CLKINT I_816 @N:FP130 : | Promoting Net Eval_pfm_0_GPIO_8_M2F on CLKINT I_435 @N:FP130 : | Promoting Net wbuf_rst on CLKINT I_817 @N:FP130 : | Promoting Net Eval_pfm_0.MSS_HPMS_READY on CLKINT I_436 @N:FP130 : | Promoting Net Eval_pfm_0.CoreConfigP_0_APB_S_PRESET_N on CLKINT I_437 @N:FP130 : | Promoting Net Eval_pfm_0.CoreConfigP_0_APB_S_PCLK on CLKINT I_438 @N:FP130 : | Promoting Net Eval_pfm_0.CoreResetP_0.sm0_areset_n_clk_base on CLKINT I_439 @N:FP130 : | Promoting Net Eval_pfm_0.CoreResetP_0.sm0_areset_n_rcosc on CLKINT I_440 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:45s; Memory used current: 235MB peak: 263MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:46s; Memory used current: 237MB peak: 263MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 2 non-gated/non-generated clock tree(s) driving 3218 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 75 clock pin(s) of sequential element(s) 0 instances converted, 75 sequential instances remain driven by gated/generated clocks ===================================================== Non-Gated/Non-Generated Clocks ===================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------------------------ ClockId0002 FCCC_0.GL0_INST CLKINT 3198 text_process_0.end_proc ClockId0003 Eval_pfm_0.OSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 20 Eval_pfm_0.CoreResetP_0.count_ddr[13] ========================================================================================================================================== ======================================================================================== Gated/Generated Clocks ========================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST MSS_025 75 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_025 ========================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:48s; CPU Time elapsed 0h:00m:47s; Memory used current: 190MB peak: 263MB) Writing Analyst data base C:\Users\tkorak\Documents\IAIK_Work\AsconOnMicrosemi\Eval_pfm\synthesis\synwork\Eval_pfm_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:50s; CPU Time elapsed 0h:00m:48s; Memory used current: 227MB peak: 263MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:52s; CPU Time elapsed 0h:00m:50s; Memory used current: 229MB peak: 263MB) Start final timing analysis (Real Time elapsed 0h:00m:53s; CPU Time elapsed 0h:00m:50s; Memory used current: 225MB peak: 263MB) @W:MT246 : eval_pfm_top_osc_0_osc.vhd(48) | Blackbox XTLOSC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : eval_pfm_top_fccc_0_fccc.vhd(106) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FCCC_0.GL0_net" @W:MT420 : | Found inferred clock Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Eval_pfm_0.OSC_0.N_RCOSC_25_50MHZ_CLKOUT" @W:MT420 : | Found inferred clock Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Eval_pfm_0.Eval_pfm_MSS_0.FIC_2_APB_M_PCLK" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Wed Dec 28 09:29:21 2016 # Top view: Eval_pfm_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 0.915 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 128.9 MHz 10.000 7.755 1.209 inferred Inferred_clkgroup_1 Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock 100.0 MHz 372.7 MHz 10.000 2.683 7.317 inferred Inferred_clkgroup_2 Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 110.1 MHz 10.000 9.085 0.915 inferred Inferred_clkgroup_0 System 100.0 MHz 895.2 MHz 10.000 1.117 8.883 system system_clkgroup ================================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ System System | 10.000 8.883 | No paths - | No paths - | No paths - System Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock | 10.000 8.622 | No paths - | No paths - | No paths - Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock | 10.000 0.915 | No paths - | No paths - | No paths - Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 2.245 | No paths - | 5.000 2.688 | 5.000 1.209 Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 10.000 7.317 | No paths - | No paths - | No paths - ============================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreConfigP_0.psel Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.108 1.209 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[1] CoreConfigP_0_MDDR_APBmslave_PRDATA[1] 5.233 2.245 Eval_pfm_0.CoreConfigP_0.state[1] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.087 2.688 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[8] CoreConfigP_0_MDDR_APBmslave_PRDATA[8] 5.507 2.691 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[13] CoreConfigP_0_MDDR_APBmslave_PRDATA[13] 5.481 2.717 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[14] CoreConfigP_0_MDDR_APBmslave_PRDATA[14] 5.377 2.821 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[5] CoreConfigP_0_MDDR_APBmslave_PRDATA[5] 5.375 2.823 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[15] CoreConfigP_0_MDDR_APBmslave_PRDATA[15] 5.370 2.828 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[3] CoreConfigP_0_MDDR_APBmslave_PRDATA[3] 5.369 2.829 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PRDATA[0] CoreConfigP_0_MDDR_APBmslave_PRDATA[0] 5.340 2.858 ================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_025 MDDR_FABRIC_PSEL CoreConfigP_0_MDDR_APBmslave_PSELx 3.853 1.209 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PREADY_0 Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0 4.662 1.571 Eval_pfm_0.CoreConfigP_0.state[1] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D state_ns[1] 4.745 1.708 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[16] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[16] 4.745 1.712 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[0] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata_N_9_i_0 4.745 1.776 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[2] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[2] 4.745 1.776 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[3] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[3] 4.745 1.776 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[4] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[4] 4.745 1.776 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[5] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[5] 4.745 1.776 Eval_pfm_0.CoreConfigP_0.FIC_2_APB_M_PRDATA_0[6] Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[6] 4.745 1.776 ===================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 1.147 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.853 - Propagation time: 2.644 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.209 Number of logic level(s): 1 Starting point: Eval_pfm_0.CoreConfigP_0.psel / Q Ending point: Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST / MDDR_FABRIC_PSEL The start point is clocked by Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK_MDDR_APB Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreConfigP_0.psel SLE Q Out 0.108 0.108 - psel Net - - 1.106 - 22 Eval_pfm_0.CoreConfigP_0.MDDR_PSEL_0 CFG4 D In - 1.214 - Eval_pfm_0.CoreConfigP_0.MDDR_PSEL_0 CFG4 Y Out 0.288 1.502 - CoreConfigP_0_MDDR_APBmslave_PSELx Net - - 1.142 - 19 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST MSS_025 MDDR_FABRIC_PSEL In - 2.644 - ====================================================================================================================== Total path delay (propagation time + setup) of 3.791 is 1.543(40.7%) logic and 2.248(59.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreResetP_0.count_ddr[0] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[0] 0.108 7.317 Eval_pfm_0.CoreResetP_0.count_ddr[1] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[1] 0.108 7.392 Eval_pfm_0.CoreResetP_0.count_ddr[2] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[2] 0.108 7.408 Eval_pfm_0.CoreResetP_0.count_ddr[3] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[3] 0.108 7.425 Eval_pfm_0.CoreResetP_0.count_ddr[4] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[4] 0.108 7.441 Eval_pfm_0.CoreResetP_0.count_ddr[5] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[5] 0.108 7.457 Eval_pfm_0.CoreResetP_0.count_ddr[6] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[6] 0.108 7.473 Eval_pfm_0.CoreResetP_0.count_ddr[7] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[7] 0.108 7.490 Eval_pfm_0.CoreResetP_0.count_ddr[8] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[8] 0.108 7.506 Eval_pfm_0.CoreResetP_0.count_ddr[9] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE Q count_ddr[9] 0.108 7.522 ========================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreResetP_0.count_ddr[13] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[13] 9.745 7.317 Eval_pfm_0.CoreResetP_0.count_ddr[12] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[12] 9.745 7.333 Eval_pfm_0.CoreResetP_0.count_ddr[11] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[11] 9.745 7.350 Eval_pfm_0.CoreResetP_0.count_ddr[10] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[10] 9.745 7.366 Eval_pfm_0.CoreResetP_0.count_ddr[9] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[9] 9.745 7.382 Eval_pfm_0.CoreResetP_0.count_ddr[8] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[8] 9.745 7.399 Eval_pfm_0.CoreResetP_0.count_ddr[7] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[7] 9.745 7.415 Eval_pfm_0.CoreResetP_0.count_ddr[6] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[6] 9.745 7.431 Eval_pfm_0.CoreResetP_0.count_ddr[5] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[5] 9.745 7.447 Eval_pfm_0.CoreResetP_0.count_ddr[4] Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock SLE D count_ddr_s[4] 9.745 7.464 =============================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 2.428 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.317 Number of logic level(s): 14 Starting point: Eval_pfm_0.CoreResetP_0.count_ddr[0] / Q Ending point: Eval_pfm_0.CoreResetP_0.count_ddr[13] / D The start point is clocked by Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK The end point is clocked by Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreResetP_0.count_ddr[0] SLE Q Out 0.108 0.108 - count_ddr[0] Net - - 0.733 - 3 Eval_pfm_0.CoreResetP_0.count_ddr_s_434 ARI1 B In - 0.841 - Eval_pfm_0.CoreResetP_0.count_ddr_s_434 ARI1 FCO Out 0.201 1.042 - count_ddr_s_434_FCO Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[1] ARI1 FCI In - 1.042 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[1] ARI1 FCO Out 0.016 1.058 - count_ddr_cry[1] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[2] ARI1 FCI In - 1.058 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[2] ARI1 FCO Out 0.016 1.075 - count_ddr_cry[2] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[3] ARI1 FCI In - 1.075 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[3] ARI1 FCO Out 0.016 1.091 - count_ddr_cry[3] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[4] ARI1 FCI In - 1.091 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[4] ARI1 FCO Out 0.016 1.107 - count_ddr_cry[4] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[5] ARI1 FCI In - 1.107 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[5] ARI1 FCO Out 0.016 1.123 - count_ddr_cry[5] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[6] ARI1 FCI In - 1.123 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[6] ARI1 FCO Out 0.016 1.140 - count_ddr_cry[6] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[7] ARI1 FCI In - 1.140 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[7] ARI1 FCO Out 0.016 1.156 - count_ddr_cry[7] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[8] ARI1 FCI In - 1.156 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[8] ARI1 FCO Out 0.016 1.172 - count_ddr_cry[8] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[9] ARI1 FCI In - 1.172 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[9] ARI1 FCO Out 0.016 1.189 - count_ddr_cry[9] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[10] ARI1 FCI In - 1.189 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[10] ARI1 FCO Out 0.016 1.205 - count_ddr_cry[10] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[11] ARI1 FCI In - 1.205 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[11] ARI1 FCO Out 0.016 1.221 - count_ddr_cry[11] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_cry[12] ARI1 FCI In - 1.221 - Eval_pfm_0.CoreResetP_0.count_ddr_cry[12] ARI1 FCO Out 0.016 1.238 - count_ddr_cry[12] Net - - 0.000 - 1 Eval_pfm_0.CoreResetP_0.count_ddr_s[13] ARI1 FCI In - 1.238 - Eval_pfm_0.CoreResetP_0.count_ddr_s[13] ARI1 S Out 0.073 1.311 - count_ddr_s[13] Net - - 1.117 - 1 Eval_pfm_0.CoreResetP_0.count_ddr[13] SLE D In - 2.428 - ======================================================================================================== Total path delay (propagation time + setup) of 2.683 is 0.833(31.0%) logic and 1.850(69.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 F_HM0_ADDR[12] Eval_pfm_MSS_0_FIC_0_AHB_MASTER_HADDR[12] 2.500 0.915 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 F_HM0_ADDR[13] Eval_pfm_MSS_0_FIC_0_AHB_MASTER_HADDR[13] 2.540 0.953 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 SPI0_SS1_MGPIO8A_H2F_B SPI0_SS1_MGPIO8A_H2F_B 2.852 0.987 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 F_AWREADY_HREADYOUT0 CoreAHBLite_1_AHBmslave16_HREADY 2.956 1.183 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 F_HM0_ADDR[14] Eval_pfm_MSS_0_FIC_0_AHB_MASTER_HADDR[14] 2.507 1.258 Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock MSS_025 F_HM0_TRANS1 Eval_pfm_MSS_0_FIC_0_AHB_MASTER_HTRANS[1] 2.552 1.336 Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt_fast[13] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt_fast[13] 0.108 1.375 Eval_pfm_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[1] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[1] 0.108 1.383 Eval_pfm_0.CoreAHBLite_1.matrix4x16.masterstage_0.SDATASELInt_fast[11] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt_fast[11] 0.108 1.423 Eval_pfm_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[2] 0.108 1.478 ===================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------- ctrl_0.i_ahb_reg.ahb_state[1] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D ahb_state_ns[1] 9.745 0.915 ctrl_0.wbytes[31] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D un1_wsize_reg_iv[31] 9.745 0.987 ctrl_0.wbytes[30] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE D un1_wsize_reg_iv[30] 9.745 1.003 ctrl_0.i_ahb_reg.int_addr[0] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[1] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[2] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[3] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[4] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[5] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ctrl_0.i_ahb_reg.int_addr[6] Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock SLE SLn N_7650_i 9.662 1.012 ================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 8.829 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.915 Number of logic level(s): 6 Starting point: Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[12] Ending point: ctrl_0.i_ahb_reg.ahb_state[1] / D The start point is clocked by Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.Eval_pfm_MSS_0.MSS_ADLIB_INST MSS_025 F_HM0_ADDR[12] Out 2.500 2.500 - Eval_pfm_MSS_0_FIC_0_AHB_MASTER_HADDR[12] Net - - 1.123 - 2 Eval_pfm_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[12] CFG2 A In - 3.623 - Eval_pfm_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[12] CFG2 Y Out 0.077 3.700 - M0GATEDHADDR[12] Net - - 1.004 - 10 Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.MASTERADDRINPROG_i_a2_1[0] CFG4 D In - 4.704 - Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.MASTERADDRINPROG_i_a2_1[0] CFG4 Y Out 0.326 5.030 - MASTERADDRINPROG_i_a2_1[0] Net - - 0.556 - 1 Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.MASTERADDRINPROG_i_a2[0] CFG4 C In - 5.586 - Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.MASTERADDRINPROG_i_a2[0] CFG4 Y Out 0.223 5.809 - masterAddrClockEnable_sx_1 Net - - 0.745 - 5 Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.hsel2 CFG4 D In - 6.554 - Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.hsel2 CFG4 Y Out 0.326 6.880 - hsel2 Net - - 0.556 - 1 Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.hsel2_RNITVJT CFG4 D In - 7.436 - Eval_pfm_0.CoreAHBLite_0.matrix4x16.slavestage_0.hsel2_RNITVJT CFG4 Y Out 0.288 7.723 - Eval_pfm_0_AHBmslave0_HWRITE Net - - 0.630 - 2 ctrl_0.i_ahb_reg.ahb_state_ns_0_a2_0_a3[1] CFG4 D In - 8.354 - ctrl_0.i_ahb_reg.ahb_state_ns_0_a2_0_a3[1] CFG4 Y Out 0.317 8.671 - ahb_state_ns[1] Net - - 0.159 - 1 ctrl_0.i_ahb_reg.ahb_state[1] SLE D In - 8.829 - ===================================================================================================================================================================== Total path delay (propagation time + setup) of 9.085 is 4.313(47.5%) logic and 4.772(52.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- FCCC_0.CCC_INST System CCC LOCK FCCC_0_LOCK 0.000 8.622 OSC_0.I_XTLOSC System XTLOSC CLKOUT OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 0.000 8.883 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- Eval_pfm_0.CoreResetP_0.fpll_lock_q1 System SLE D FCCC_0_LOCK 9.745 8.622 FCCC_0.CCC_INST System CCC XTLOSC OSC_0_XTLOSC_CCC_OUT_XTLOSC_CCC 10.000 8.883 ================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.255 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.745 - Propagation time: 1.123 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 8.622 Number of logic level(s): 0 Starting point: FCCC_0.CCC_INST / LOCK Ending point: Eval_pfm_0.CoreResetP_0.fpll_lock_q1 / D The start point is clocked by System [rising] The end point is clocked by Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- FCCC_0.CCC_INST CCC LOCK Out 0.000 0.000 - FCCC_0_LOCK Net - - 1.123 - 2 Eval_pfm_0.CoreResetP_0.fpll_lock_q1 SLE D In - 1.123 - =================================================================================================== Total path delay (propagation time + setup) of 1.378 is 0.255(18.5%) logic and 1.123(81.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:53s; CPU Time elapsed 0h:00m:51s; Memory used current: 225MB peak: 263MB) Finished timing report (Real Time elapsed 0h:00m:53s; CPU Time elapsed 0h:00m:51s; Memory used current: 225MB peak: 263MB) --------------------------------------- Resource Usage Report for Eval_pfm_top Mapping to part: m2s025fbga484std Cell usage: CCC 1 use CLKINT 9 uses MSS_025 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use XTLOSC 1 use CFG1 9 uses CFG2 549 uses CFG3 1573 uses CFG4 2277 uses Carry primitives used for arithmetic functions: ARI1 189 uses Sequential Cells: SLE 3291 uses DSP Blocks: 0 I/O ports: 68 I/O primitives: 65 BIBUF 28 uses INBUF 5 uses OUTBUF 29 uses OUTBUF_DIFF 1 use TRIBUFF 2 uses Global Clock Buffers: 9 Total LUTs: 4597 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 3291 + 0 + 0 + 0 = 3291; Total number of LUTs after P&R: 4597 + 0 + 0 + 0 = 4597; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:54s; CPU Time elapsed 0h:00m:51s; Memory used current: 65MB peak: 263MB) Process took 0h:00m:54s realtime, 0h:00m:51s cputime # Wed Dec 28 09:29:22 2016 ###########################################################]