Project Settings |
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Project Name | Eval_pfm_top_syn | Implementation Name | synthesis |
Top Module | work.Eval_pfm_top | Retiming | 0 |
Resource Sharing | 1 | Fanout Guide | 10000 |
Disable I/O Insertion | 0 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
78 |
539 |
0 |
- |
0m:13s |
- |
28.12.2016 09:28:18 |
(premap) | Complete |
65 |
13 |
0 |
0m:02s |
0m:03s |
169MB |
28.12.2016 09:28:27 |
(fpga_mapper) | Complete |
71 |
53 |
0 |
0m:51s |
0m:54s |
263MB |
28.12.2016 09:29:22 |
Multi-srs Generator |
Complete | | | | 0m:03s | | | 28.12.2016 09:28:22 |
Area Summary |
| |
Carry Cells | 189 |
Sequential Cells | 3291 |
DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 65 |
Global Clock Buffers | 9 |
LUTs
(total_luts) | 4597 |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
Eval_pfm_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 128.9 MHz | 1.209 |
Eval_pfm_OSC_0_OSC|N_RCOSC_25_50MHZ_CLKOUT_inferred_clock | 100.0 MHz | 372.7 MHz | 7.317 |
Eval_pfm_top_FCCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 110.1 MHz | 0.915 |
System | 100.0 MHz | 895.2 MHz | 8.883 |
Optimizations Summary |
Combined Clock Conversion | 2 / 1 |
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